The present invention relates to a semiconductor memory, and more specifically it relates to a semiconductor memory that enables dimensional adjustment by using a fuse which can be cut with a laser beam.
Circuits that constitute a semiconductor memory include circuits achieved by arraying a plurality of identically structured circuits (iterated circuits) such as an input/output circuit and a read amplifier circuit. As higher integration, further miniaturization and multiple-output structuring have been achieved in semiconductor memories in recent years, the use of iterated circuits in semiconductor memory has been on the rise.
An FIB (focused ion beam) apparatus is employed to machine an iterated circuit in the prior art. The FIB apparatus cuts wiring by taking advantage of the sputtering phenomenon that occurs when an ion beam is irradiated. For instance, the FIB apparatus is employed to adjust the width of the gate of a transistor that constitutes a pre-driver circuit for driving an output buffer circuit in the output circuit of a random access memory (RAM).
However, the number of iterated circuits in a semiconductor memory has been on the rise due to the higher integration, further miniaturization and multiple-output structuring achieved in the semiconductor memory in recent years. The increase in the number of machining areas resulting from the increase in the number of iterated circuits poses problems with respect to the machining process implemented by utilizing the FIB apparatus in the prior art in that the length of machining time is bound to increase, that the machining accuracy is compromised and that the device evaluation becomes a lengthy procedure.
An object of the present invention, which has been completed by addressing the problems of the semiconductor memory in the prior art discussed above, is to provide a new and improved semiconductor memory that facilitates machining of iterated circuits to solve the problems of the prior art such as the great length of time required for machining, the compromised machining accuracy and the lengthy device evaluation process.
Another object of the present invention is to provide a new and improved semiconductor memory that achieves a smaller layout area to minimize any increase within the chip area.
In order to achieve the objects described above, a first semiconductor memory according to the present invention is provided with a plurality of output circuits and a fuse circuit commonly connected to the output circuits. The fuse circuit outputs an output signal to each output circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, and the output circuits are each provided with an output buffer circuit unit and a pre-driver circuit unit that drives the output buffer circuit unit, with the driving capability of the pre-driver circuit unit determined by the output signal provided by the fuse circuit.
A second semiconductor memory according to the present invention is provided with a plurality of output circuits and a plurality of fuse circuits each connected to one of the output circuits. Each fuse circuit outputs an output signal to the corresponding output circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, and the output circuits are each provided with an output buffer circuit unit and a pre-driver circuit unit that drives the output buffer circuit unit, with the driving capability of the pre-driver circuit unit determined by the output signal provided by the corresponding fuse circuit.
A third semiconductor memory according to the present invention is provided with a plurality of amplifier circuits and a fuse circuit connected to the individual amplifier circuits. The fuse circuit outputs an output signal to each amplifier circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the amplifying capability of each amplifier circuit determined by the output signal provided by the fuse circuit.
A fourth semiconductor memory according to the present invention is provided with a plurality of amplifier circuits and a plurality of fuse circuits each connected to one of the amplifier circuits. Each fuse circuit outputs an output signal to the corresponding amplifier circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the amplifying capability of the amplifier circuit determined by the output signal provided by the fuse circuit.
A fifth semiconductor memory according to the present invention is provided with a plurality of delay circuits and a fuse circuit connected to the individual delay circuits. The fuse circuit outputs an output signal to each delay circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the delay time generated by each of the delay circuits determined by the output signal provided by the fuse circuit.
A sixth semiconductor memory according to the present invention is provided with a plurality of delay circuits and a plurality of fuse circuits each connected to one of the delay circuits. Each fuse circuit outputs an output signal to the corresponding delay circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the delay time generated by the delay circuit determined by the output signal provided by the fuse circuit.
A seventh semiconductor memory according to the present invention is provided with a plurality of input first-stage circuits and a fuse circuit connected to the individual input first-stage circuits. The fuse circuit outputs an output signal to each input first-stage circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the input voltage margin of the input first-stage circuit determined by the output signal provided by the fuse circuit.
An eighth semiconductor memory according to the present invention is provided with a plurality of input first-stage circuits and a plurality of fuse circuits each connected to one of the input first-stage circuits. Each fuse circuit outputs an output signal to the corresponding input first-stage circuit, the signal level of which is fixed to one signal level or another signal level depending upon whether or not a fuse in the circuit is disconnected, with the input voltage margin of the input first-stage circuit determined by the output signal provided by the fuse circuit.